The issue is one of software compatibility, xScale has no 26 bit mode, so is not (yet) RiscOS compatible. The best MD and Millipede can do is make sure their boards are electrically and physically able to take the processor when it and 32 bit RiscOS does arrive - I am certain they will.

I would assume that the Omega has a 64 bit bus because the RAM it uses is 64 bit, I would hope that the de/multiplexing
would be for the StrongArm not the X-Scale.

The first processors on Imago and Omega will be SA-110 (32 bits) a vacant spot will be left for the xScale. The problem is that Omega (according to pundits) has been in the works for nearly 3 years, at a time when NO ONE knew a 64bit data bus ARM was on the way. If they've had the foresight to build a 64bit bus in as the co-processor data bus then there is no problem. Millipede for their part were adapting the Imago board for xScale, but it was not yet decided (as of the Epson show) if the co-processor bus would be 32 or 64 bits wide.

Interestingly the reason the xScale has a 64 bit databus (as does the ARM10 and all ARM V5TE processors) is so that TWO Arm instructions can be fetched in one clock cycle. The ARM then performs a neat trick, if one of the instructions is a branch it can "predict" what instruction to use (the second in the load buffer) or the one to be loaded from the branch address. Fewer pipeline stalls neat !

Multiplex/DeMux is only required if the processor data bus is 32 bits wide and an ARM10/xScale is fitted (if the data bus is 64 bits wide to the daughterboard then no MUX/DEMUX is required). Although it complexifies things (for the PCB designer) a 64bit bus is the preferred option.

Otherwise the logic is that there is a MUX/DEMUX pair on both sides of the databus, the xScale "sees" a 64 bit data bus (the DEMUX/MUX pair on the Daughterboard), the memory sees a 64 bit databus (a DEMUX/MUX pair on the motherboard) but between the mux/demux pairs is a 32 bit wide channel clocked at TWICE the speed of the memory. Designing a 266MHz channel like this would be a real pain in the head but if done the processor would not see a performance hit at all and neither would the RAM. This scheme requires designing a fast bus and interface system operating at 266MHz (or above) this is not a trivial task, but it has been done before (the EV-6 bus on the Athlon runs at 200MHz).

Where this scheme falls down is (if) in 2 years time 266MHz DDR RAM is to be used as main ram it is unlikely that the MUX/DEMUX channel will cope (a future bottleneck). All in all its a scheme probably best avoided.

[Edited by ams at 19:26, 23/1/2001]

[Edited by ams at 19:31, 23/1/2001]

better get the notebook and wait how the omega turns out to be.. and if that's ok, buy it anyway (hmm, maybe win the lottery.. :-))

I'd be in the same position myself, I would love a laptop, but an ARM7500 doesn't have the same appeal as an xScale (or even a StrongARM).

Here's a thought apparently the SA-1110 has an on chip LCD controller (but is not 26bit compatible) but is effectively a 233MHz StrongARM as well. Perhaps when ROL get the 32 bit version out that may allow RiscStation to build a really FAST portable rather than an A7000 with an LCD screen.

By the way just in case they don't - best of luck with the Lottery Marco !